Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern

ABSTRACT

A semiconductor random access memory device is subjected to a parallel testing operation to see whether or not a defective memory cell is incorporated in the semiconductor random access memory device; in the parallel testing operation, a test bit of logic &#34;1&#34; level is sequentially written into a first predetermined address of each of data storage blocks by changing a column address, then, a test bit of logic &#34;0&#34; level is written into a second predetermined address of each of the data storage blocks by changing the column address again, and the write-in operation is repeated so as to form a checker-like bit pattern in each data storage block; after the formation of the test pattern, the test bits are sequentially read out from the first predetermined address of the data storage blocks to a read and write data bus system to see whether or not any one of the test bits are inconsistent with the other test bits so that the parallel testing is carried out on various bit patterns.

FIELD OF THE INVENTION

This invention relates to a semiconductor memory device and, moreparticularly, to a dynamic random access memory device having a paralleltesting architecture on the memory cells.

DESCRIPTION OF THE RELATED ART

The dynamic random access memory device is progressively increasing thememory cells integrated therein, and time period for a diagnosis isprolonged together with the integration density. One of the approachesfor accelerating the diagnosis is known as a parallel testingarchitecture where a plurality of memory cells more than input test bitsare simultaneously checked to see whether or not a defective memory cellis incorporated in the memory cell array.

A typical example of the dynamic random access memory device isdisclosed in Japanese Unexamined Publication No. 61-261895, and FIG. 1illustrates the circuit arrangement disclosed therein. A memory cellarray 1 is implemented by a plurality of addressable memory cells, andis associated with a multiplexer 2, a data output unit 3 and a paralleltesting unit 4. The memory cell array 1 is electrically connectedthrough a plurality of data lines 5 with a multiplexer 2, and themultiplexer 2 is responsive to address signals indicative of one of thedata lines 5 for transferring a data bit on the selected data line tothe output unit 3.

The output unit 3 comprises a shifter 3a and an output buffer 3belectrically connected through an output pad 3b with an output pin (notshown). The shifter 3a has two input nodes respectively connected withthe output node of the multiplexer 2 and the output node of the paralleltesting unit 4, and is responsive to a mode control signal P1 fortransferring the selected data bit or a judging signal to the outputbuffer 3b. Namely, the shifter 3a comprises an inverter 3d for producingthe complementary signal of the mode control signal P1, two OR gates 3eand 3f selectively enabled with the mode control signal P1 of logic "0"level and the complementary signal thereof, and an AND gate 3g connectedwith the output nodes of the OR gates 3e and 3f. The output node of themultiplexer 2 and the output node of the parallel testing unit 4 arerespectively connected with the other input nodes of the respective ORgates 3e and 3 f, and, for this reason, the selected data bit or thejudging signal is transferred through the enabled OR gate 3e or 3f tothe output buffer 3b.

The parallel testing unit 4 is implemented by an exclusive-OR gate, andis electrically connected through auxiliary data lines 6 with the memorycell array 1. A data signal P2 indicative of a test bit is furthersupplied to the exclusive-OR gate 4, and the exclusive-OR gate 4compares the read-out data bits and the data signal P2 with one anotherfor producing the judging signal.

The prior art random access memory device thus arranged selectivelyenters a standard mode and a parallel testing mode of operation. Whilethe mode control signal P1 is in logic "1" level indicative of theparallel testing mode, the OR gate 3e is disabled, and the other OR gate3f is enabled with the complementary signal of logic "0" level. The ORgate 3e produces the output signal of logic "1" level regardless of theoutput signal of the multiplexer 2.

The test bit indicated by the test signal P2 is written into the memorycells of the array 1, and the test bits are read out from a row ofmemory cells to the data lines 5. The test bits are transferred throughthe auxiliary data lines 6 to the exclusive-OR gate 4, and theexclusive-OR gate 4 checks the read-out test bits and the original testbit represented by the test signal P2 to see whether or not any one ofthe test bits is different in logic level from the other test bits. Ifall of the read-out test bits and the original test bit are consistentwith one another, the row of memory cells are diagnosed to be excellent,and the exclusive-OR gate 4 produces the judging signal of logic "0"level. The enabled OR gate 3f transfers the judging signal through theAND gate 3g to the output buffer 3b. On the other hand, if any one ofthe read-out test bits and the original test bit is inconsistent withthe other test bits, the exclusive-OR gate acknowledges a defectivememory cell in the row of memory cells, and shifts the judging signal tologic "1" level. The judging signal is also transferred through theenabled OR gate 3f and the AND gate 3g to the output buffer 3b. Ineither case, the judging signal is output from the output buffer 3bthrough the output pad 3c to the output pin.

When the mode signal P1 is changed to logic "0" level, the prior artdynamic random access memory device enters the standard mode, and the ORgate 3e is enabled. However, the other OR gate 3f is disabled with thecomplementary signal of the mode control signal P1. In this situation,data bits are read out from a row of memory cells to the data lines 5,and the multiplexer 2 selects one of the data bits-in response to theaddress signals. The selected data bit is transferred through theenabled OR gate 3e and the AND gate 3g to the output buffer 3b. Theoutput buffer 3b produces an output data signal from the selected databit, and the output data signal is output through the output pad 3c tothe output pin. Therefore, the output pad 3c and, accordingly, theoutput pin are shared between the parallel testing mode and the standardmode.

The prior art parallel testing unit 4 accelerates the testing operationon the memory cells without any output pad exclusively used. However,the prior art parallel testing architecture concurrently examines only arow of memory cells, and is expected to repeat the parallel testingoperation on the individual rows. Therefore, if the rows of memory cellsare increased, the prior art parallel testing architecture is lesseffective.

Moreover, it is necessary to write a test bit of either logic level intothe memory cells. If a test bit of logic "1" level and a test bit oflogic "0" level are alternately written into the memory cells, theexclusive-OR can not discriminate the test bit read out from thedefective memory cell. Therefore, the prior art parallel testingarchitecture sets a limit on the patter of test bits stored in thememory cells.

Japanese Unexamined Publication No. 63-37894 discloses a paralleltesting architecture. However, the parallel testing architecture issimilar to that described hereinbefore, and no further description isincorporated in this specification.

Another prior art parallel testing architecture is disclosed in "A 64Mbit DRAM with Merged Match-line Test Architecture by Yamada et al,Technical Report of Electronic Information Communication Society, vol.90, No. 496, SDM90-199, pages 27 to 33, March 1991. FIG. 2 illustratesan essential part of the prior art dynamic random access memory devicedisclosed in the technical report. Although write-in circuits areincorporated in the prior art dynamic random access memory device, FIG.2 is focused on read-out/comparing circuits.

The prior art dynamic random access memory device comprises a memorycell array 11, and the memory cell array 11 is constituted by memorycells M10, M11, M12, M20, M21 and M22 represented by small circles. Thememory cells are selectively connected with bit line pairs B00/B01,B10/B11 and B20/B21, and word lines W0 and W1 allow data bits to beselectively read out from and written into the memory cells M10 to M22.An address decoder/word line driver 12 is responsive to addresspredecoded signals, and drives one of the word lines W0 and W1 to activelevel.

A plurality of sense amplifiers SA0, SA1 and SA2 are respectivelyconnected with the bit line pairs B00/B01 to B20/B21, and increasepotential differences on the bit line pairs B00/B01 to B20/B21,respectively.

A plurality of read-out/comparing circuits RC0, RC1 and RC2 are furtherassociated with the bit line pairs B00/B01 to B20/B21, and are connectedbetween the bit line pairs B00/B01 to B20/B21 and a pair of data linesD0 and D1. Each of the read-out/comparing circuits RC0 to RC2 comprisestwo series combinations of n-channel enhancement type switchingtransistors Q1/Q2 and Q3/Q4 connected between the data lines D0/D1 andthe ground voltage line. The read-out/comparing circuits RC0 to RC2 areassociated with the selecting lines YS0 to YS2, and the n-channelenhancement type switching transistors Q1 and Q3 are gated by theassociated selecting line YS0, YS1 or YS2. The other n-channelenhancement type switching transistors Q2 and Q4 are respectively gatedby the associated bit lines B00/B01, B10/B11 or B20/B21, and theread-out/comparing circuits RC0 to RC2 selectively connect the datalines D0 and D1 with the ground voltage line.

The data lines D0 and D1 are connected with a precharging circuit 13,and an error detection circuit 14 monitors the data lines D0 and D1. Inthis instance, the error detection circuit 14 is implemented by a NORgate.

The prior art dynamic random access memory device thus arranged behavesin a test mode as follows. A test bit is firstly written into all of thememory cells M10 to M22, and the bit line pairs B00/B01 to B20/B21 andthe data lines D0/D1 are precharged to an intermediate voltage levelbetween high and low voltage levels. The data lines D0 and D1 areprecharged to the high voltage level, and the address decoder/word linedriver 12 drives one of the word lines W0 and W1 to the active level.

The test bits are read out from the memory cells coupled with the wordline driven to the active level, and small potential differences takeplace on the associated bit line pairs B00/B01 to B20/B21, respectively.The sense amplifiers SA0 to SA2 are activated, and increase thepotential differences on the bit line pairs B00/B01 to B20/B21.

In the test mode, since all of the selecting lines YS0 to YS2 go up tothe high voltage level, the n-channel enhancement type switchingtransistors Q1/Q3 turn on, and all of the read-out/comparing circuitsRC0 to RC2 are simultaneously enabled for providing current paths to theground voltage line.

If the memory cells coupled with the selected word line are excellent,the test bits read out therefrom are identical in logic level, and then-channel enhancement type switching transistors either Q2 or Q4 turn onfor electrically connecting the associated data line D0 or D1 with theground voltage line. However, the other data line D1 or D0 is isolatedfrom the ground voltage line, and maintains the high voltage level. As aresult, the high voltage level or logic "1" level and the low voltagelevel or logic "0" level are supplied to the NOR gate 14, and the NORgate 14 keeps an error detecting signal at inactive low voltage level.

However, if a defective memory cell is incorporated in the selectedmemory cells, the test bit read out therefrom is complementary to thetest bits read out from the other excellent memory cells. The test bitread out from the defective memory cell, by way of example, causes then-channel enhancement type switching transistor Q2 of the associatedread-out/comparing circuit to turn on, and the other test bits allow then-channel enhancement type switching transistors Q4 of the associatedread-out/comparing circuits to turn on. As a result, both data lines D0and D1 are electrically connected with the ground voltage line, and thelow voltage levels or logic "0" levels are supplied to the NOR gate 14.Then, the NOR gate 14 produces the error signal of the high voltagelevel, and an analyst diagnoses the product to be defective on the basisof the error signal.

Thus, the second prior art parallel testing architecture alsoaccelerates the diagnosis, and a circuit arrangement for the paralleltesting may be simpler than that of the first prior art example.However, the second prior art parallel testing architecture merelyallows the read-out/comparing circuits RC0 to RC2 to check the test bitsread out from only one row of memory cells, and is expected to repeatthe testing operation as similar to the first prior art parallel testingarchitecture.

Moreover, it is necessary for the test bits read out from a row ofmemory cells to be in either logic level, and the second prior artparallel testing architecture also sets the limit on the pattern of testbits.

In general, if data bits stored in adjacent memory cells arecomplementary to each other, the data bits tend to be affected, and adefective memory cell inverts one of the data bits. 2In order to screenout such a defective memory cell, it is necessary to alternately write atest bit of logic "1" level and a test bit of logic "0" into the memorycells. However, both first and second prior art parallel testingarchitectures can not examine the memory cells storing such an alternatebit pattern through the parallel testing operation.

SUMMARY OF THE INVENTION

It is therefore an important object of the present invention to providea dynamic random access memory device which carries out a paralleltesting operation with various patterns of test bits.

To accomplish the object, the present invention proposes to sequentiallywrite a test bit into predetermined data storage blocks and another testbit into other predetermined data storage blocks for forming a checkerpattern of the test bits.

In accordance with one aspect of the present invention, there isprovided a semiconductor dynamic random access memory device having astandard mode of operation for selectively writing data bits andselectively reading out the data bits, and a parallel testing mode ofoperation for sequentially writing test bits and sequentially readingout the test bits, comprising: a) a plurality of data storage blocksarranged in rows and columns, each of the plurality of data storageblocks having a-1) a plurality of addressable memory cells forrespectively storing the data bits or the test bits, a-2) a plurality ofsub-word lines selectively connected with the plurality of addressablememory cells, and selectively driven to an active level so that selectedmemory cells of the plurality of addressable memory cells becomeaccessible, a-3) a partial decoder unit connected with the plurality ofsub-word lines, and driving one of the sub-word lines to the activelevel, and a-4) a plurality of sense amplifier circuits selectivelyconnected with the plurality of addressable memory cells for amplifyingpotential differences indicative of the data bits or the test bits; b) aplurality of block selecting lines respectively associated with thecolumns of data storage blocks, and selectively driven to an activelevel for enabling the partial decoder units of a column of data storageblocks; c) a column address decoder unit connected with the plurality ofblock selecting lines, and responsive to first address bits for drivingone of the block selecting lines to the active level; d) a plurality ofmain word line groups respectively associated with the rows of theplurality of data storage blocks, and each connected with the partialdecoder units of the data storage blocks in the associated row forallowing the partial decoder unit of one of the data storage blocks inthe selected column to selectively driving the sub-word lines; e) a rowaddress decoder unit connected with the plurality of main word linegroups, and responsive to second address bits for selectively drivingone of the plurality of main word line groups to an active level; f) aplurality groups of data propagation paths respectively associated withthe columns of data storage blocks, each group of data propagation pathsbeing connected with the sense amplifier circuits of each of the datastorage blocks in the associated column for transferring the potentialdifferences; g) an input and output means operative to receive an inputdata and output an output data in the standard mode and to sequentiallyreceive the test bits and output a diagnostic signal in the paralleltesting mode, and having a read and write bus system for propagating theinput data, the output data and the test bits in the form of potentialdifference; h) a plurality of line selecting means respectivelyassociated with the plurality groups of data propagation paths, and eachselectively connecting the data propagation paths of the associatedgroup with the read and write bus system, the block selecting linesbeing sequentially driven to the active level for writing each of thetest bits into predetermined data storage blocks in the parallel testingmode, the block selecting lines being sequentially driven to the activelevel for reading out the data bits from the predetermined data storageblocks in the parallel testing mode; and i) a diagnostic meansassociated with the input and output means, and monitoring potentiallevels on the read and write bus system in the parallel testing mode tosee whether or not the test bits sequentially read out from thepredetermined data storage blocks are identical in logic level forproducing the diagnostic signal indicative of consistence orinconsistence.

In accordance with another aspect of the present invention, there isprovided a semiconductor dynamic random access memory device having astandard mode of operation for selectively writing data bits andselectively reading out the data bits, and a parallel testing mode ofoperation for sequentially writing test bits and sequentially readingout the test bits, comprising: a) a plurality of data storage blocksarranged in rows and columns, each of the plurality of data storageblocks having a-1) a plurality of addressable memory cells forrespectively storing the data bits or the test bits, a-2) a plurality ofsub-word lines selectively connected with the plurality of addressablememory cells, and selectively driven to an active level so that selectedmemory cells of the plurality of addressable memory cells becomeaccessible, a-3) a partial decoder unit connected with the plurality ofsub-word lines, and driving one of the sub-word lines to the activelevel, and a-4) a plurality of sense amplifier circuits selectivelyconnected with the plurality of addressable memory cells for amplifyingpotential differences indicative of the data bits or the test bits; b) aplurality of block selecting lines respectively associated with thecolumns of data storage blocks, and selectively driven to an activelevel for enabling the partial decoder units of a column of data storageblocks; c) a column address decoder unit connected with the plurality ofblock selecting lines, and responsive to first address bits for drivingone of the block selecting lines to the active level; d) a plurality ofmain word line groups respectively associated with the rows of theplurality of data storage blocks, and each connected with the partialdecoder units of the data storage blocks in the associated row forallowing the partial decoder unit of one of the data storage blocks inthe selected column to selectively driving the sub-word lines; e) a rowaddress decoder unit connected with the plurality of main word linegroups, and responsive to second address bits for selectively drivingone of the plurality of main word line groups to an active level, therow address decoder unit being operative to sequentially drive theplurality of main word line groups in the parallel testing mode forwring each of the test bits into predetermined data storage blocks, therow address decoder unit further being operative to sequentially drivethe plurality of main word line groups in the parallel testing mode sothat the test bits are read out from the predetermined data storageblocks; f) a plurality groups of data propagation paths respectivelyassociated with the columns of data storage blocks, each group of datapropagation paths being connected with the sense amplifier circuits ofeach of the data storage blocks in the associated column fortransferring the potential differences; g) an input and output meansoperative to receive an input data and output an output data in thestandard mode and to sequentially receive the test bits and output adiagnostic signal in the parallel testing mode, and having a read andwrite bus system for propagating the input data, the output data and thetest bits in the form of potential difference; h) a plurality of lineselecting means respectively associated with the plurality groups ofdata propagation paths, and each selectively connecting the datapropagation paths of the associated group with the read and write bussystem; and i) a diagnostic means associated with the input and outputmeans, and monitoring potential levels on the read and write bus systemin the parallel testing mode to see whether or not the test bitssequentially read out from the predetermined data storage blocks areidentical in logic level for producing the diagnostic signal indicativeof consistence or inconsistence.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the dynamic random access memory deviceaccording to the present invention will be more clearly understood fromthe following description taken in conjunction with the accompanyingdrawings in which:

FIG. 1 is a circuit diagram showing the first prior art dynamic randomaccess memory device;

FIG. 2 is a circuit diagram showing the essential part of the secondprior art dynamic random access memory device;

FIG. 3 is a circuit diagram showing the circuit arrangement of a dynamicrandom access memory device according to the present invention;

FIG. 4 is a circuit diagram showing the circuit arrangement of a datastorage block associated with a selector unit according to the presentinvention;

FIG. 5 is a circuit diagram showing the arrangement of a data amplifierincorporated in the dynamic random access memory device according to thepresent invention;

FIG. 6 is a logic diagram showing a diagnostic circuit incorporated inthe dynamic random access memory device according to the presentinvention;

FIG. 7 is a timing chart showing a read-out phase in a parallel-bittesting sequence according to the present invention;

FIG. 8 is a timing chart showing a read-out phase in anotherparallel-bit testing sequence according to the present invention; and

FIG. 9 is a circuit diagram showing the arrangement of another dynamicrandom access memory device according to the present invention,

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

Referring to FIG. 3 of the drawings, a dynamic random access memorydevice embodying the present invention is fabricated on a semiconductorchip 20, and comprises a plurality of data storage blocks MB00, MB01, .. . , MB0n, MB10, MB11, . . . , MB1n, MBm0, MBm1, . . . and MBmnarranged in rows and columns.

A plurality groups of main word lines MWL01 to MWL0i, MWL11 to MWL1i, .. . and MWLm1 to MWLmi are respectively associated with the rows of datastorage blocks MB00 to MBmn, and primary row addresses are respectivelyassigned to the rows of data storage blocks MB00 to MBmn and,accordingly, to the main word line groups MWL01/MWL0i to MWLm1/MWLmi. Arow address decoder 21 selects one of the main word line groupsMWL01/MWL0i to MWLm1/MWLmi and a row of data storage blocks associatedtherewith.

A plurality of block selecting lines BS0, BS1, . . . and BSn are furtherassociated with the columns of data storage blocks MB00 to MBmn, andcolumn addresses are respectively assigned to the columns of datastorage blocks MB00 to MBmn and, accordingly, the block selecting linesBS0 to BSn. A column address decoder 22 selectively drives the blockselecting lines BS0 to BSn, and selects a column of data storage blocks.Therefore, each of the data storage blocks MB00 to MBmn is selected byone of the main word line groups MWL01 to MWL0i to MWLm1 to MWLmi andone of the block selecting lines BS0 to BSn.

A plurality groups of bit line pairs BL01/BL0j, BL11/BL1, . . . andBLn1/BLnj are respectively associated with the data storage blocks MB00to MBmn, and the bit line pairs BL01/BL0j, BL11/BL1 j, . . . orBLn1/BLnj are grouped for each column of data storage blocks MB00 toMBmn (see FIG. 4). Each group of the bit line pairs BL01, . .. ,BL0j, .. . , BL11 , . . . , BLn1, . . . or BLnj consitute a data propagationpath. However, the bit line pair BL01 to the bit line pair BL0j may beshared between one of the columns of the data storage blocks.

The plurality groups of bit line pairs BL01/BL0j to BLn1/BLnj areterminated at a plurality of selector units 230, 231, . . . and 23n,respectively, and each selector unit 230, . . . or 23n is shared betweenthe groups of bit line pairs BL01/BL0j, . . . or BLn1/BLnj associatedwith one of the columns of data storage blocks. The selector units 230to 23n are controlled by a line address decoder 24. Line addresses arerespectively assigned to the bit line pairs of each group, and the lineaddress decoder 24 causes each of the selector units 230 to 23n toelectrically connect two of the bit line pairs of one of the groups ofbit line pairs BL01/BL0j, . . . or BLn1/BLnj with an associated dataamplifier 250, 251, . . . or 25n through data line pairs DL01/DL02,DL11/Dl12, . . . and DLn1/DLn2. A read/write data bus system RWB0/RWB1is shared between the data amplifier units 250 to 25n, and electricallyconnects two input and output units 26a and 26b with the data amplifierunits 250 to 25n. The input and output units 26a ad 26b are connectedwith data input and output pins 27a and 27b, respectively.

The plurality groups of bit line pairs BL01/BL0j to BLn1/BLnj arefurther connected with a plurality of precharging units 280, 281, . . .and 28n, and the plurality of precharging units 280 to 28n respectivelycharge the bit line pairs BL01/BL0j to BLn1/BLnj to an intermediatevoltage level in response to a precharge control signal PC1 before everyaccess.

The data storage blocks MB00 to MBmn are similar in arrangement to oneanother, and the data storage block MB00 is, by way of example,described hereinbelow with reference to FIG. 4. The data storage blockMB00 largely comprises memory cells M11, M1a, . . . , M1b, M1j, Mk1,Mka, . . . , Mkb and Mkj, a partial row address decoder WD connectedwith the main word lines MWL01 to MWL0i for selectively driving subwardlines SWL1 to SWLk and a plurality of sense amplifier circuits SA1, SAa,. . . , SAb and SAj associated with the bit line pairs BL01, BL0a, . . ., BL0b and BL0j. Secondary row addresses are respectively assigned tothe sub-word lines SWL1 to SWLk and, accordingly, to the rows of memorycells M11 to Mkj. On the other hand, the bit line pairs are broken downinto two sub-groups BL01 to BL0a and BL0b to BL0j, and line addressesare assigned to the respective bit line pairs BL01 to BL0a and therespective bit line pairs BL0b to BL0j. Therefore, each line address isindicative of two bit line pairs in one of the bit line groups BL01/BL0jto BLn1/BLnj. The memory cells M11 to Mkj are of a one-transistorone-capacitor type, and a data bit is stored therein in the form ofelectric charge.

The columns of memory cells M11 to Mkj are respectively associated withthe bit line pairs BL01 to BL0j of the associated group, and the drainnodes of the memory cells in each column are alternately connected withthe bit lines of the associated pair.

The sub-word lines SWL1 to SWLk are respectively associated with therows of memory cells M11 to Mkj, and each of the sub-word lines SWL1 toSWLk are coupled with the gate of the memory cells in the associatedrow. The partial row address decoder WD is enabled with the associatedblock selecting line BS0, and becomes responsive to the associated mainword lines MWL01 to MWLmi for driving one of the sub-word lines SWL1 toSWLk to an active level.

The memory cells coupled with the sub-word line driven to the activelevel become conductive with the bit lines of the associated prechargedpairs BL01 to BL0j, and potential differences indicative of the storeddata bits take place on the bit line pairs BL01 to BL0j, respectively.

The sense amplifier circuits SA1 to SAj are concurrently powered withhigh and low power voltage levels, and develop or increase the potentialdifferences indicative of data bits.

The selector unit 230 comprises two multiplexers 230a and 230b and twogroups of data selectors 230c and 230d, and the multiplexers 230a and230b and the data selector groups 230c and 230d are under the control ofthe line address decoder 24. The bit line pairs of each group BL01 BL0jare divided into two sub-groups, i.e., the bit line pairs BL01 to BL0aand the bit line pairs BL0b to BL0j. The multiplexer 230a and the dataselector 230c select a bit line pair from the first sub-groups, andelectrically connect the data line pair DL01 with the selected bit linepair. Similarly, the other multiplexer 230b and the other data selectorgroup 230d select a bit line pair from the second sub-groups, andelectrically connects the data line pair DL02 with the selected bit linepair.

The other selector units 231 to 23n are similar in arrangement to theselector unit 230, and no further description is incorporatedhereinbelow.

The data amplifier unit 250 has two data amplifiers 250a and 250b, andare connected between the read/write data bus PWB0 and the data linepair DL01 and between the read/write data bus PWB1 and the data linepair DL02, respectively.

As will be illustrated in FIG. 5, each of the data amplifiers 250a and250b comprises a write amplifier 250c and a read amplifier 250d, and theread amplifier 250d is associated with two n-channel enhancement typedischarging transistors 250e and 250f. The write amplifier 250 isoperative to increase a potential difference indicative of a write-indata bit on the read/write data bus PWB0 or PWB1, and supplies theincreased potential difference to the data line pair DL01 or DL02. Onthe other hand, the read amplifier 250d is responsive to a potentialdifference indicative of a read-out data bit on the data line pair DL01or DL02, and produces gate control signals complementary to each other.The n-channel enhancement type discharging transistors 250e and 250fhave respective source-to-drain paths connected between the read/writebus PWB0 or PWB1 and a ground voltage line. The gate control signals aresupplied from the read amplifier 250d to the gate electrodes of then-channel enhancement type discharging transistors 250e and 250f, andthe n-channel enhancement type discharging transistors 250e and 250fcomplementarily turn on and off depending upon the read-out data bit.

Turing back to FIG. 4, a precharging circuit 29 is connected with theread/write data buses PWB0 and PWB1, and charges the read/write databuses PWB0 and PWB1 to the high voltage level before the write-in databit or the read-out data bit is transferred to thereto.

The input-and-output units 26a and 26b are similar in circuitarrangement to each other, and each of the input-and-output units 26aand 26b is implemented by an input data buffer 26c and an output databuffer 26d coupled in parallel between the associated input-and-outputdata pin 27a or 27b and the read/write data bus PWB0 or PWB1. Thewrite-in data bit is supplied from the input-and-output data pin 27a or27b to the input data buffer 26c, and the input data buffer 26c producesthe potential difference on the associated read/write data bus PWB0 orPWB1 from the write-in data bit. The output data buffer 26d produces anoutput data signal or a diagnostic signal from the potential differenceon the associated read/write data bus PWB0 or PWB1 or a judging signalJG1 or JG2 supplied from a diagnostic unit 30 described hereinbelow indetail.

The diagnostic unit 30 is implemented by two comparator circuits 20a and20b, and the two comparator circuits 30a and 30b respectively monitorthe read/write data bus PWB0 and the read/write data bus PWB1 forproducing the judging signals JG1 and JG2, respectively.

As shown in FIG. 6, each of the comparator circuits 30a and 30bcomprises an inverter 30c supplied with a test enable signal TE1, and aNOR gate 30d supplied with the voltage levels on the associatedread/write data bus PWB0 or PWB1 as well as the complementary testenable signal. The NOR gate 30d is enabled with the complementary testenable signal of the low voltage level corresponding to logic "0" level,and checks the voltage levels on the associated read/write data bus PWB0or PWB1 to see whether or not the voltage levels supplied thereto aredifferent from each other if the data lines of the associated read/writedata bus PWB0 or PWB1 are different in voltage level, i.e., the highvoltage level and the low voltage level, each of the comparator circuits30a and 30b produces the judging signal JG1 or JG2 indicative ofconsistence between test bits. However, if both data lines are in thelow voltage level, each of the comparator circuits 30a and 30b shiftsthe judging signal JG1 or JG2 to the high voltage level indicative ofinconsistence between the test bits.

When the judging signal from the associated comparator 30a or 30b isindicative of the inconsistence, the output data buffer 26d produces thediagnostic signal indicative of a defect. On the other hand, if thejudging signal remains in the low voltage level indicative of theconsistence, the output data buffer supplies the diagnostic signalindicative of excellence.

Turning back to FIG. 3, the dynamic random access memory device furthercomprises an address buffer unit 31 connected with address pins forexternal address bits indicative of primary and secondary row addresses,a column address and a line address, and the address buffer unit 31produces address predecoded signals for the row address decoder 21, thecolumn address decoder 22 and the line address decoder 24.

A timing generating unit 32 is incorporated in the dynamic random accessmemory device, and is connected with control signal pins for externalcontrol signals such as, for example, a row address strobe signal, acolumn address strobe signal and a write enable signal. The timinggenerating unit 32 is responsive to the external control signals, andsequentially produces internal timing signals for controlling a write-insequence and a read-out sequence.

The dynamic random access memory device further comprises a test modeentry circuit 33, and the test mode entry circuit 33 causes the dynamicrandom access memory device to enter a test mode for diagnosing thecomponents thereof. In detail, when predetermined external controlsignals change in potential level into a predetermined pattern, the testmode entry circuit 33 acknowledges the test mode, and selectivelyproduces test enable signals depending upon predetermined address bits.Namely, bit patterns of the predetermined address bits are respectivelyindicative of internal test sequences, and the test mode entry circuit33 discriminates a requested test sequence on the basis of thepredetermined address bits. One of the bit patterns is indicative of aparallel-bit testing sequence described hereinlater, and the test modeentry circuit 33 produces the test enable signal TE1 in the parallel-bittesting sequence.

In this instance, the data amplifier units 250 to 25n, the read andwrite data bus system PWB0 and PWB1, the input and output data bufferunits 26a and 26b, the input and output data pins 27a, the prechargingcircuit 29 and the n-channel enhancement type discharging transistors250e and 250f as a whole constitute an input and output means, and theselector units 230 to 230n and the line address decoder 24 form incombination a plurality of line selecting means.

Although other systems such as an auto-refreshing system and a powersupply system are further incorporated in the dynamic random accessmemory device according to the present invention, these systems are notillustrated in the attached drawings, because they are less importantfor understanding the present invention.

The dynamic random access memory device thus arranged selectively entersa standard mode and the test mode. In the standard mode, the dynamicrandom access memory device carries out the write-in sequence forwriting write-in data bits into one of the data storage blocks MB00 toMBmn and the read-out sequence for reading out read-out data bits fromone of the data storage blocks MB00 to MBmn. Although a refreshingsequence is further carried out in the standard mode, no description ismade thereon.

Assuming now that the predetermined external control signals do notchange into the predetermined pattern, the dynamic random access memorydevice remains in the standard mode, and external address bits aresequentially latched by the address buffer unit 31 in synchronism withthe external control signals such as address strobe signals.

The address buffer unit 31 produces a set of address predecoded signalsindicative of a column address, and the column address decoder 22acknowledges the row address for driving one of the block selectingsignals BS0 to BSn to the active level. As a result, the block selectingsignal driven to the active level simultaneously enables the partial rowaddress decoders WD incorporated in one of the columns of data storageblocks.

The address buffer unit 31 further produces another set of addresspredecoded signals indicative of primary and secondary row addresses,and the row address decoder 21 selectively drives one of the groups ofmain word lines MWL01/MWL0i to MWLm1/MWLmi associated with the row ofdata storage blocks assigned the primary row address. However, the othergroups of main word lines remain inactive.

Only one data storage block enabled with the block selecting signal isresponsive to the selected group of main word lines, and drives one ofthe sub-word lines assigned the secondary row address to an activelevel. A row of memory cells connected with the selected sub-word lineare electrically connected with the associated bit line pairs, and databits stored therein are read out thereto for producing potentialdifferences. The potential differences are amplified by the associatedsense amplifier circuits SA1 to SAj.

Write-in data bits are supplied to the input and output data pins 27aand 27b, and are transferred to the input data buffer circuits 26c. Theprecharging circuit 29 has already charged the data buses PWB0 and PWB1to the high voltage level. The input data buffer circuits 26c producespotential differences from the write-in data bits, and the potentialdifferences are propagated through the data buses PWB0 and PWB1 to thewrite amplifiers 250c of the data amplifier units 250a and 250bincorporated in each data amplifier 250, . . . or 25n, respectively. Thewrite amplifiers 250c of the data amplifier units 250a and 250b amplifythe potential differences on the data buses PWB0 and PWB1.

The address buffer unit 31 further produces yet another set of addresspredecoded signals from the address bits indicative of a line address,and the line address decoder 24 causes each of the selector units 230 to23n to connect the data buses PWB0 and PWB1 with two groups of bit linepairs assigned the line address. If the address predecoded signals areindicative of the leftmost bit line pairs of the two sub-groups, the bitline pairs BL01, the bit line pairs BL0b, . . . , and the bit line pairsBLn1 and the bit line pairs BLnb are coupled with the data buses PWB0and PWB1.

Then, the potential differences indicative of the write-in data bits aretransferred from the data amplifier units 250a and 250b to the selectedbit line pairs associated with the selected data storage block. Thepotential differences indicative of the write-in data bits either invertor keep the potential differences already produced on the selected bitline pairs, and the write-in data bits are stored in the memory cellsassigned the row, column and line addresses. The potential differenceson the other bit line pairs associated with the selected data storageblock are restored in the original memory cells. Even if the potentialdifferences are further transferred to the bit line pairs associatedwith non-selected data storage blocks, the write-in data bits are neverstored in the corresponding memory cells of the non-selected datastorage blocks, because any sub-word line does not allow the memorycells to be conducted with the bit line pairs.

In the read-out sequence, after the potential differences on the bitsline pairs are amplified by the sense amplifiers SA1 to SAj, theselector unit associated with the selected data storage unit connectsthe two bit line pairs assigned to the line address with the readamplifiers 250d of the data amplifier units 250a and 250b, and selectsread-out data bits from the data bits stored in the selected datastorage block. The read amplifiers 250d selectively discharge data buslines of the data buses PWB0 and PWB1 already precharged to the highvoltage level, and transfers the potential differences indicative of theread-out data bits to the data buses PWB0 and PWB1, respectively. Thedata buses PWB0 and PWB1 propagate the potential differences to theoutput data buffers 26d of the associated input and output data bufferunits 26a and 26b, and the output data buffers 26d produce the outputdata signals indicative of the read-out data bits, respectively. Theoutput data signals are supplied to the input-and-output data pins 27aand 27b.

However, in the standard mode, the test mode entry circuit 33 does notproduce any test enable signal, and the diagnostic unit 30 is neverresponsive to the potential differences on the data buses PWB0 and PWB1.

On the other hand, if the external control signals change into thepredetermined pattern in the presence of the address bits indicative ofthe parallel-bit testing sequence, the test mode entry circuit 33acknowledges the parallel-bit testing sequence, and the dynamic randomaccess memory device is subjected to the parallel-bit test.

An external diagnostic system (not shown) is expected to alternatelyarrange a test bit of logic "1" level and a test bit of logic "0" levelover the data storage blocks MB00 to MBmn in a checker-like bit pattern.If the checker-like bit pattern have a first row of test bits "1010 . .. 1010", the second row of test bits have the bit string "0101 . . .0101", and the bit string of the third row is "1010 . . . 1010".

First, the test bits of logic "1" level are applied to theinput-and-output data pins 27a and 27b, respectively, and the externaladdress bits select the memory cells M11 and M1b from the data storageblock MB00. Although the test bits are transferred from the dataamplifier units 250 to 25n through the selector units 230 to 23n to thebit line pairs BL01/BL0b to BLn1/BLnb assigned the line address, thetest bits of logic "1" level are written into the memory cells M11 andM1b of the selected data storage block MB00 through the write-insequence described hereinbefore, because the column address decoder andthe row address decoder 22 and 21 activate the block selecting line BS0only. The external address bits indicative of the column address are,then, changed to the block selecting line BS1, and are latched by theaddress buffer unit 31. The column address decoder 22 changes theactivated block selecting line from BS0 to BS1, and the test bits oflogic "1" level already transferred to the bit line pairs BL11 and BL1bare stored in the memory cells M11 and M1b of the data storage blockMB01.

In this way, the external address bits indicative of the column addressare changed from the block selecting line BS0 to the block selectingline BSn, and the test bits of logic "1" level are sequentially writteninto the memory cells M11 and M1b of the data storage blocks MB00 toMB0n without any change of the line address and the primary andsecondary row addresses. The test bit of logic "1" level are writteninto the 2n memory cells during a single access by only changing thecolumn address.

Subsequently, test bits of logic "0" level are applied to theinput-and-output data pins 27a and 27b, and the line address is changedfrom the bit line pairs BL01/BL0b . . . BLn1/BLnb to the next bit linepairs. However, the primary and secondary row addresses are unchanged,and the column address returns to the block selecting line BS0. Thewrite-in sequence is carried out again, and the test bits of logic "0"level is written into the memory cells next to the memory cells M11 andM1b of the data storage block MB00. The write-in sequence is repeatedfor the memory cells adjacent to the memory cells M11 and M1b bychanging the column address from the block selecting line BS0 to theblock selecting line BSn, and the test bit of logic "0" level are storedin the memory cells adjacent to the memory cells storing the test bitsof logic "1" level.

Thus, the test bits of logic "1" level and the test bits of logic "0"level are alternately applied to the input-and-output data pins 27a and27b, and are written into the rows of memory cells assigned the sameprimary and secondary row addresses by changing the column address andthe line address.

Subsequently, when the line address and the column address return to theinitial values, the secondary row address is changed from the row ofmemory cells M11 to M1j to the next row of memory cells. The test bitsof logic "0" and test bits of logic "1" level are alternately applied tothe input-and-output data pins 27a and 27b, and the test bit of logic"0" level and the test bit of logic "1" level are alternately writteninto the memory cells of the data storage blocks MB00 to MB0n assignedthe selected secondary row address by changing the column address andthe line address. The write-in sequence is repeated for all of the rowsof memory cells incorporated in the data storage blocks MB00 to MB0n.

When all of the memory cells of the data storage blocks MB00 to MB0nstore the test bit of logic "1" level and the test bit of logic "0"level, each test bit of logic "1" level is surrounded by the test bitsof logic "0" level, and each test bit of logic "0" level is alsosurrounded by the test bits of logic "1" level. In other words, the testbits stored in each data storage block form a checker-like bit pattern.

Upon completion of the checker-like bit pattern in the first row of datastorage blocks MB00 to MB0n, the primary row address is changed from therow of data storage blocks MB00 to MB0n to the data storage blocks MB10to MB1n. The above described write-in sequence is repeated for the datastorage blocks MB10 to MB1n, and the checker-like bit pattern is formedin the data storage blocks MB10 to MB1n.

When the test bits are written into the memory cells Mka and Mkj of therow of the data storage blocks MBm0 to MBmn, the test bit of logic "1"level and the test bit of logic "0" level have been alternately writteninto all of the data storage blocks MB00 to MBmn in the checker-like bitpattern, and the memory cells will be examined whether to keep the testbits or to lose them. If a memory cell loses the test bit, the read-outbit is changed in logic level.

After formation of the checker-like bit pattern in all of the datastorage blocks MB00 to MBmn, the test bits stored therein aresequentially read out through the read-out sequence as follows. In thefollowing description, the memory cells M11 and M1b of the data storageblock MB01 are assumed to be defective, and the test bits are invertedto logic "0" level. However, if a memory cell is excellent, the test bitstored therein is not inverted.

First, the precharging circuits 280 to 28n charge all of the bit linepairs BL01/BL0j to BLn1/BLnj to the intermediate voltage level, and theprecharging circuit 29 charges the read and write data buses PWB0 andPWB1 to the high voltage level. As shown in FIG. 7, the primary andsecondary row addresses, the line address and the column address areindicative of the memory cells M11 and M1b of the data storage blockMB00 at time t1, and the test bits of logic "1" are read-out from thememory cells M11 and M1b of the data storage blocks MB00 through theread-out sequence. The non-inverted test bits are amplified by the senseamplifier circuits SA1 to SAj, and are transferred to the readamplifiers 250d. The read amplifiers 250d are responsive to thenon-inverted test bits, and each read amplifier 250d discharges one ofthe data bus line of the associated read and write data bus PWB0 or PWB1at time t2. However, the other data bus lines remain in the high voltagelevels.

The column address is changed from the block selecting line BS0 to thesubsequent block selecting line BS1 at time t3, and the inverted bits oflogic "0" are read out from the memory cells M11 and M1b of the datastorage block MB01 without any precharging on the bit line pairs and theread and write data buses PWB0/PWB1. After the amplification, theinverted test bits are transferred to the read amplifiers 250d, and theinverted test bits causes the read amplifiers 250d to discharge theother data bus lines at time t4. As a result, all of the data bus linesbecome low.

The column address is sequentially changed, and the non-inverted testbits are sequentially read out from the memory cells M11 and M1b of theother data storage blocks associated with the main word line group MWL01to MWL0i without any precharging on the bit line pairs and on the readand write data buses PWB0/PWB1. While the primary and secondary rowaddresses and the line addresses are being fixed, the read and writedata bus system PWB0/PWB1 are not precharged again, and the data buslines are maintained in the low voltage level. The column address isfinally changed to the block selecting line BSn at time t5, and thenon-inverted test bits are transferred to the read amplifiers 250d.Then, the test enable signal TE1 goes up at time t6, and theexclusive-OR gates 30d are enabled with the complementary signal of thetest enable signal. All of the data bus lines have been discharged, andlogic "0" bits are supplied from the data bus lines of the associatedbus to the exclusive-OR gate 30d. Then, the exclusive-OR gates 30dproduce the judging signals JG1 and JG2 of the high voltage levelindicative of the defective memory cells. The judging signals JG1 andJG2 are supplied to the output data buffers 26d, and the diagnosticsignals of the low voltage level are produced and supplied to the inputand output data pins 27a and 27b at time t7. The diagnostic signals ofthe low voltage level are indicative of the defective memory cells M11and M1b. Thus, the 2n bits are sequentially checked to see whether ornot they are consistent in a single access, and the diagnostic signalsreports the results of the parallel-bit testing sequence to the outsidethereof.

The primary and secondary row addresses are maintained, and the lineaddress is changed from the M11 and M1b to the next or adjacent memorycells in the same row. Although the bit line pairs are not precharged,the read and write data buses PWB0/PWB1 are precharged by theprecharging circuit 29 again. The column address returns to the blockselecting line BS0. The non-inverted test bits of logic "0" level areread out from the adjacent memory cells of the data storage block MB00through the read-out sequence at time t11, and are transferred to theread amplifiers 250d after the amplification by the sense amplifiercircuits SA1 to SAj. After the line address is changed, the read andwrite data buses PWB0 and PWB1 are charged to the high voltage levelagain. Then, each of the read amplifiers 250d discharges one of the databus lines of the associated bus at time t12, and allows the other databus line to remain in the high voltage level.

The column address is changed to the block selecting line BS1 at timet13, and the non-inverted test bits are read out from the adjacentmemory cells of the data storage block MB01 without any precharging onthe bit line pairs and the read and write data buses PWB0/PWB1. The readamplifiers 250d continues to keep the other data bus lines in the highvoltage level.

Finally, the column address is changed to the block selecting line BSnat time t14, and the non-inverted test bits are read out from theadjacent memory cells of the data storage block MB0n without anyprecharging on the bit lines and the read and write data busesPWB0/PWB1, and are transferred to the read amplifiers 250d. The readamplifiers 250d keep the other data bus lines in the high voltage level,and the high voltage level and the low voltage level are supplied fromeach read and write data bus to the associated exclusive-OR gate 30d.The test enable signal TE1 goes up to the high voltage level at timet15, and the exclusive-OR gates 30d produce the judging signals JG1 andJG2 of the high voltage level indicative of the excellent memory cells.The output data buffers 26d produces the diagnostic signals of the highvoltage level at time t16, and supply the diagnostic signals to theinput and output data pins 27a and 27b. The 2n test bits aresequentially checked in the parallel-bit testing sequence by changingthe column address.

Thus, while the column address and the line address are being changed,the primary and secondary row addresses are fixed. However, when theline address returns to the memory cells M11 and M1b, the secondary rowaddress is incremented, and the parallel-bit testing sequence isrepeated by changing the column address and the line address asdescribed hereinbefore.

When the secondary row address returns to the subword line SWL1, theprimary row address is incremented, and the parallel-bit testingsequence is repeated by changing the column address, the line addressand the secondary row address. When the primary row address returns tothe main word lines MWL01/MWL0i, all of the test bits are checked to seewhether to be consistent or not.

Thus, all of the memory cells are checked to see whether or not adefective memory cell is incorporated in the data storage blocks MB00 toMBmn. If defective memory cells are incorporated, a redundancytechnology rescues the dynamic random access memory device.

As will be appreciated from the foregoing description, the dynamicrandom access memory device is subjected to the parallel-bit testingsequence in the presence of the test bits arranged in the checker-likebit pattern, and a defective memory cell is perfectly screened out forenhancing the reliability thereof.

Second Embodiment

A dynamic random access memory device implementing the second embodimentis similar to that of the first embodiment except for the parallel-bittesting sequence, and, for this reason, description on the circuitarrangement is not incorporated hereinbelow. The references designatingthe components of the first embodiment are used in the followingdescription for better understanding.

Assuming now that the dynamic random access memory device enters thetest mode, an external diagnostic system alternately arrange a test bitof logic "1" level and a test bit of logic "0" level over the datastorage blocks MB00 to MBmn in the checker-like bit pattern as similarto the first embodiment.

First, the test bits of logic "1" level are applied to theinput-and-output data pins 27a and 27b, respectively, and the externaladdress bits select the memory cells M11 and M1b from the data storageblock MB00. Although the test bits are transferred from the dataamplifier units 250 to 25n through the selector units 230 to 23n to thebit line pairs BL01/BL0b to BLn1/BLnb in the form of potentialdifference, the test bits of logic "1" level are written into theselected memory cells M11 and M1b of the data storage block MB00 throughthe write-in sequence. The external address bits indicative of theprimary row address are, then, changed from the main word line groupMWL01/MWL0i to the main word line group MWL11/MWL1i, and are latched bythe address buffer unit 31. The row address decoder 21 changes theselected main word line group from MWL01/MWL0i to MWL11/MW1i, and thetest bits of logic "1" level already transferred to the bit line pairsBL01 and BL0b are stored in the memory cells M11 and M1b of the datastorage block MB10.

In this way, the external address bits indicative of the primary rowaddress are changed from the main word line group MWL01/MWL0i to themain word line group MWLm1/MWLmi, and the test bits of logic "1" levelare written into the memory cells M11 and M1b of the data storage blocksMB00 to MBm0 without any change of the secondary row address, the lineaddress and the column address. The test bit of logic "1" level arewritten into the 2m memory cells during a single access by only changingthe primary row address.

Subsequently, test bits of logic "0" level are applied to theinput-and-output data pins 27a and 27b, and the line address is changedfrom the bit line pairs BL01/BL0b to the next bit line pairs. Theprimary row address returns to the main word line group MWL01/MWL0i.However, the secondary row address and the column address are unchanged.The write-in sequence is carried out again, and the test bits of logic"0" level is written into the memory cells next to the memory cells M11and M1b of the data storage block MB00. The write-in sequence isrepeated for the memory cells adjacent to the memory cells M1 and M1b bychanging the primary row address from the main word line groupMWL01/MWL0i to the main word line group MWLm1/MWLmi, and the test bit oflogic "0" level are stored in the memory cells adjacent to the memorycells storing the test bits of logic "1" level of the data storageblocks MB00 to MBm0.

Thus, the test bits of logic "1" level and the test bits of logic "0"level are alternately applied to the input-and-output data pins 27a and27b, and are written into the rows of memory cells assigned the samesecondary row address and the column address by changing the primary rowaddress and the line address.

Subsequently, when the line address and the primary row address returnto the initial values, the secondary row address is changed from the rowof memory cells M11 to M1j to the next row of memory cells. The testbits of logic "0" and test bits of logic "1" level are alternatelyapplied to the input-and-output data pins 27a and 27b, and the test bitof logic "0" level and the test bit of logic "1" level are alternatelywritten into the memory cells of the data storage blocks MB00 to MBm0assigned the same secondary row address by changing the primary rowaddress and the line address. The write-in sequence is repeated for allof the rows of memory cells incorporated in the data storage blocks MB00to MBm0.

When all of the memory cells of the data storage blocks MB00 to MBm0store the test bit of logic "1" level and the test bit of logic "0"level, each test bit of logic "1" level is surrounded by the test bitsof logic "0" level, and each test bit of logic "0" level is alsosurrounded by the test bits of logic "1" level. The checker-like bitpattern is formed in the data storage blocks MB00 to MBm0.

Upon completion of the checker-like bit pattern in the first column ofdata storage blocks MB00 to MBm0, the column address is changed from theblock selecting line BS0 to the block selecting line BS1, and theprimary and secondary row addresses and the line address return to theinitial values, respectively. In other words, the primary and secondaryrow addresses, the line address and the column address select the memorycells M11 to M1b of the data storage block MB01. The above describedwrite-in sequence is repeated for the data storage blocks MB01 to MBm1by changing the primary row address, the line address and the secondaryrow address, and the checker-like bit pattern is formed in the datastorage blocks MB01 to MBm1.

When the test bits are written into the memory cells Mka and Mkj of thecolumn of the data storage blocks MB0n to MBmn, the test bit of logic"1" level and the test bit of logic "0" level have been alternatelywritten into all of the data storage blocks MB00 to MBmn in thechecker-like bit pattern, and the memory cells will be examined whetherto keep the test bits or to lose them. If a memory cell loses the testbit, the read-out bit is changed in logic level.

After formation of the checker-like bit pattern in all of the datastorage blocks MB00 to MBmn, the test bits stored therein aresequentially read out through the read-out sequence as follows. In thefollowing description, the memory cells M11 and M1b of the data storageblock MB10 are assumed to be defective, and the test bits are invertedto logic "0" level.

Referring to FIG. 8, the primary and secondary row addresses, the lineaddress and the column address are indicative of the memory cells M11and M1b of the data storage block MB00 at time t21, and the prechargingcircuit 280 charges the bit line pairs BL01/BL0j to the intermediatevoltage level. The precharging circuit 29 charges the read and writedata buses PWB0 and PWB1. The test bits of logic "1" level are read-outfrom the memory cells M11 and M1b of the data storage blocks MB00through the read-out sequence. The non-inverted test bits of logic "1"level are amplified by the sense amplifier circuits SA1 to SAj, and aretransferred to the read amplifiers 250d. The read amplifiers 250d areresponsive to the non-inverted test bits, and each read amplifier 250ddischarges one of the data bus line of the associated read and writedata bus PWB0 or PWB1 at time t22. However, the other data bus linesremain in the high voltage levels.

After the precharging on the bit line pairs BL01/BL0j, the primary rowaddress is changed from the main word line group MWL01/MWL0i to thesubsequent main word line group MWL11/MWL1i at time t23, and theinverted bits of logic "0" are read out from the memory cells M11 andM1b of the data storage block MB10. However, the read and write databuses PWB0/PWB1 are not precharged. After the amplification by the senseamplifiers SA1 to SAj, the inverted test bits are transferred to theread amplifiers 250d, and the inverted test bits causes the readamplifiers 250d to discharge the other data bus lines at time t24. As aresult, all of the data bus lines become low.

The primary row address is sequentially changed, and the non-invertedtest bits are sequentially read out from the memory cells M11 and M1b ofthe other data storage blocks MB00 to MBm0 by changing the primary rowaddress after the precharging on the bit line pairs BL01/BL0j. While thetest bits are sequentially read out from the data storage blocks MB00 toMBm0, the read and write data bus system PWB0/PWB1 are not prechargedagain, and the data bus lines are maintained in the low voltage level.The primary row address is finally changed to the main word line groupMWLm1/MWLmi at time t25, and the non-inverted test bits are transferredto the read amplifiers 250d after the amplification by the senseamplifier circuits SA1 to SAj. Then, the test enable signal TE1 goes upat time t26, and the exclusive-OR gates 30d are enabled with thecomplementary signal of the test enable signal. All of the data buslines have been discharged, and logic "0" bits are supplied from thedata bus lines of the associated bus to the exclusive-OR gate 30d. Then,the exclusive-OR gates 30d produce the judging signals JG1 and JG2 ofthe high voltage level indicative of the defective memory cells. Thejudging signals JG1 and JG2 are supplied to the output data buffers 26d,and the diagnostic signals of the low voltage level are produced andsupplied to the input and output data pins 27a and 27b at time t27. Thediagnostic signals of the low voltage level are indicative of thedefective memory cells M11 and M1b. Thus, the 2m bits are sequentiallychecked to see whether or not they are consistent in a single access,and the diagnostic signals reports the results of the parallel-bittesting sequence to the outside thereof.

The secondary row address and the column address are maintained, and theline address is changed from the M11 and M1b to the next or adjacentmemory cells in the same row. The primary row address returns to themain word line group MWL01/MWL0i, and the read and write data busesPWB0/PWB1 are precharged again. After the bit line pairs BL01/BL0j areprecharged, the non-inverted test bits of logic "0" level are read outfrom the adjacent memory cells of the data storage block MB00 throughthe read-out sequence at time t31, and are transferred to the readamplifiers 250d after the amplification by the sense amplifier circuitsSA1 to SAj. Then, each of the read amplifiers 250d discharges one of thedata bus lines of the associated bus at time t32, and allows the otherdata bus line to remain in the high voltage level.

The primary row address is changed to the main word line groupMWL11/MWL1i at time t33, and the bit line pairs BL01/BL0j are prechargedagain. However, the read and write data buses PWB0/PWB1 are notprecharged. The non-inverted test bits of logic "0" level are read outfrom the adjacent memory cells of the data storage block MB10, and areamplified by the sense amplifier circuits SA1 to SAj. The readamplifiers 250d continues to keep the other data bus lines in the highvoltage level.

Finally, the column address is changed to the main word line groupMWLm1/MWLmi at time t34, and the bit line pairs BL01/BL0j areprecharged. However, the read and write data buses PWB0/PWB1 are notprecharged. The non-inverted test bits are read out from the adjacentmemory cells of the data storage block MBm0, and are transferred to theread amplifiers 250d after the amplification by the sense amplifiercircuits SA1 to SAj. The read amplifiers 250d keep the other data buslines in the high voltage level, and the high voltage level and the lowvoltage level are supplied from each read and write data bus to theassociated exclusive-OR gate 30d. The test enable signal TE1 goes up tothe high voltage level at time t35, and the exclusive-OR gates producethe judging signals JG1 and JG2 of the high voltage level indicative ofthe excellent memory cells. The output data buffers 26d produces thediagnostic signals of the high voltage level at time t36, and supply thediagnostic signals to the input and output data pins 27a and 27b. The 2mtest bits are sequentially checked in the next parallel-bit testingsequence by changing the primary row address.

Thus, while the primary row address and the line address are beingchanged, the secondary row address and the column address are fixed.However, when the line address returns to the memory cells M11 and M1b,the secondary row address is incremented without any change of thecolumn address, and the parallel-bit testing sequence is repeated bychanging the primary row address and the line address as describedhereinbefore.

When the secondary row address returns to the subword line SWL1, thecolumn address is incremented, and the parallel-bit testing sequence isrepeated by changing the primary row address, the line address and thesecondary row address. In this way, the parallel-bit testing sequence isrepeated by changing the primary row address, the line address, thesecondary row address and the column address, and all of the test bitsare read out from the data storage blocks MB00 to MBmn to see whether tobe consistent or inconsistent.

Thus, all of the memory cells are checked to see whether or not adefective memory cell is incorporated in the data storage blocks MB00 toMBmn. If defective memory cells are incorporated, a redundancytechnology rescues the dynamic random access memory device.

If all of the data storage blocks MB00 to MBmn are respectivelyassociated with bit line pair groups, the parallel-bit testing sequencemay be carried out by changing the primary row address without anyprecharging on the bit line pairs.

In the first and second embodiments, the checker-like bit pattern isformed over the data storage blocks MB00 to MBmn, and either column orprimary row address is sequentially changed in a single parallel-bittesting sequence. However, if test bits are alternately written intoevery row of memory cells, the secondary row address may be sequentiallychanged instead of the column address and the primary row address in thetest mode. In this instance, the test bits may be sequentially read outfrom all of the data storage blocks MB00 to MBmn in a singleparallel-bit testing sequence by changing not only the column addressbut also the secondary row address.

Third Embodiment

Turning to FIG. 9 of the drawings, another dynamic random access memorydevice embodying the present invention is fabricated on a singlesemiconductor chip 41. FIG. 9 only shows an essential part of thedynamic random access memory device, and some units such as a test modeentry circuit, an address buffer unit and a timing generator are deletedtherefrom. The dynamic random access memory device implementing thesecond embodiment is similar to the first embodiment except for datatransfer line pair groups 410 to 41m, and the other components arelabeled with the same references used in FIG. 3 without detaileddescription.

The data transfer line pair groups DLP01/DLP0j, DLP11/DLP1j, . . . andDLPm1/DLPmj, and are shared between the rows of data storage blocks MB00to MBmn, respectively. Each of the data transfer line groups isconstituted by the data transfer line pairs respectively connectedbetween the associated selector unit and the bit line pairs, andtransfers potential differences therebetween. The data transfer linepair groups DLP01/DLP0j to DLPm1/DLPmj extend in parallel to the mainword lines MWL01/MWL0i to MWLm1/MWLmi and to the sub-word lines SWL1 toSWLk, and are not overlapped with the bit line pairs BL01/BL0j toBLn1/BLnj. Thus, the data transfer line pairs DLP01/DLP0j to DLPm1/DLPmjdo not extend over the data storage blocks MB00 to MBmn, and are freefrom any capacitive coupling.

The dynamic random access memory device shown in FIG. 9 also selectivelyenters the standard mode and the test mode. However, the read-outsequence, the write-in sequence and the parallel-bit testing sequenceare similar to those of the first embodiment, and no further descriptionis incorporated hereinbelow for the sake of simplicity.

Although particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the present invention. For example, the dynamicrandom access memory device according to the present invention may forma part of an ultra large scale integration together with other functionblocks. A dynamic random access memory device may have aninput-and-output data pin associated with a single read and write databus or more than two input-and-output data pins associated with morethan two read and write data buses. Moreover, various test bit patternsare diagnosed through the parallel-bit testing sequence according to thepresent invention.

What is claimed is:
 1. A semiconductor dynamic random access memorydevice having a standard mode of operation for selectively writing databits and selectively reading out said data bits, and a parallel testingmode of operation for sequentially writing test bits and sequentiallyreading out said test bits, comprising:a) a plurality of data storageblocks arranged in rows and columns, each of said plurality of datastorage blocks havinga-1) a plurality of addressable memory cells forrespectively storing said data bits or said test bits, a-2) a pluralityof sub-word lines selectively connected with said plurality ofaddressable memory cells, and selectively driven to an active level sothat selected memory cells of said plurality of addressable memory cellsbecome accessible, a-3) a partial decoder unit connected with saidplurality of sub-word lines, and driving one of said sub-word lines tosaid active level, and a-4) a plurality of sense amplifier circuitsselectively connected with said plurality of addressable memory cellsfor amplifying potential differences representing data bits read outfrom and written into selected addressable memory cells or said testbits; b) a plurality of block selecting lines respectively associatedwith the columns of data storage blocks, and selectively driven to anactive level for enabling the partial decoder units of a column of datastorage blocks; c) a column address decoder unit connected with saidplurality of block selecting lines, and responsive to first address bitsfor driving one of said block selecting lines to said active level; d) aplurality of main word line groups respectively associated with the rowsof said plurality of data storage blocks, and each said main word linegroups connected with the partial decoder units of the data storageblocks in the associated row for allowing the partial decoder unit ofone of said data storage blocks in the selected column to selectivelydrive said sub-word lines; e) a row address decoder unit connected withsaid plurality of main word line groups, and responsive to secondaddress bits for selectively driving one of said plurality of main wordline groups to an active level; f) a plurality of groups of datapropagation paths respectively associated with said columns of datastorage blocks, each group of data propagation paths being connectedwith the sense amplifier circuits of each of the data storage blocks inthe associated column for transferring said potential differences; g) aninput and output means coupled with signal pins, and operative toreceive an input data and output an output data in said standard modeand to sequentially receive said test bits and output a diagnosticsignal in said parallel testing mode, said input and output means havinga read and write bus system for propagating said input data, said outputdata and said test bits in the form of potential difference; h) aplurality of line selecting means respectively associated with saidplurality of groups of data propagation paths, and coupled between saidplurality groups of data propagation paths and said read and write bussystem, each selectively connecting the data propagation paths of theassociated group of data propagation path with said read and write bussystem, said block selecting lines being sequentially driven to saidactive level for writing each of said test bits into predetermined datastorage blocks in said parallel testing mode, said block selecting linesbeing sequentially driven to said active level for reading out said databits from said predetermined data storage blocks in said paralleltesting mode; and i) a diagnostic means associated with said input andoutput means, and monitoring potential levels on said read and write bussystem in said parallel testing mode to see whether or not the test bitssequentially read out from said predetermined data storage blocks areidentical in logic level for producing said diagnostic signal indicativeof consistence or inconsistence.
 2. A semiconductor dynamic randomaccess memory device as set forth in claim 1, in which said input andoutput means further comprisesa precharging circuit connected with databus lines of said read and write bus system for precharging to a firstvoltage level, a plurality of discharging transistors connected betweensaid data bus lines and a line of constant voltage, and a read amplifiermeans responsive to the potential differences indicative of said outputdata or said test bits for causing said plurality of dischargingtransistors to selectively turn on, said precharging circuit beingoperative to precharge said read and write bus system before said testbits are sequentially read out from said predetermined data storageblocks in said parallel testing mode so that first predetermined databus lines of said data bus lines and the remaining data bus lines are inthe first voltage level and in the constant voltage level if all of thetest bits are consistent in logic level with each other.
 3. Asemiconductor dynamic random access memory device as set forth in claim1, further comprising a plurality of groups of data transfer line pairsrespectively associated with the rows of data storage blocks andextending between areas of a semiconductor chip,said areas beingrespectively assigned to said plurality of data storage blocks, eachgroup of data transfer line pairs being implemented by a plurality ofdata transfer line pairs, each of said transfer line pairs beingimplemented by two transfer lines, and each group of data transfer linepairs being coupled to the sense amplifier circuits of the associatedrow of data storage blocks and the associated line selecting means.
 4. Asemiconductor dynamic random access memory device having a standard modeof operation for selectively writing data bits and selectively readingout said data bits, and a parallel testing mode of operation forsequentially writing test bits and sequentially reading out said testbits, comprising:a) a plurality of data storage blocks arranged in rowsand columns, each of said plurality of data storage blocks havinga-1) aplurality of addressable memory cells for respectively storing said databits or said test bits, a-2) a plurality of sub-word lines selectivelyconnected with said plurality of addressable memory cells, andselectively driven to an active level so that selected memory cells ofsaid plurality of addressable memory cells become accessible, a-3) apartial decoder unit connected with said plurality of sub-word lines,and driving one of said sub-word lines to said active level, and a-4) aplurality of sense amplifier circuits selectively connected with saidplurality of addressable memory cells for amplifying potentialdifferences indicative of said data bits or said test bits; b) aplurality of block selecting lines respectively associated with thecolumns of data storage blocks, and selectively driven to an activelevel for enabling the partial decoder units of a column of data storageblocks; c) a column address decoder unit connected with said pluralityof block selecting lines, and responsive to first address bits fordriving one of said block selecting lines to said active level; d) aplurality of main word line groups respectively associated with the rowsof said plurality of data storage blocks, and each connected with thepartial decoder units of the data storage blocks in the associated rowfor allowing the partial decoder unit of one of said data storage blocksin the selected column to selectively drive said sub-word lines; e) arow address decoder unit connected with said plurality of main word linegroups, and responsive to second address bits for selectively drivingone of said plurality of main word line groups to an active level, saidrow address decoder unit being operative to sequentially drive saidplurality of main word line groups in said parallel testing mode forwriting each of said test bits into predetermined data storage blocks,said row address decoder unit further being operative to sequentiallydrive said plurality of main word line groups in said parallel testingmode so that the test bits are read out from said predetermined datastorage blocks; f) a plurality of groups of data propagation pathsrespectively associated with said columns of data storage blocks, eachgroup of data propagation paths being connected with the sense amplifiercircuits of each of the data storage blocks in the associated column fortransferring said potential differences; g) an input and output meansoperative to receive an input data and output an output data in saidstandard mode and to sequentially receive said test bits and output adiagnostic signal in said parallel testing mode, and having a read andwrite bus system for propagating said input data, said output data andsaid test bits in the form of potential difference; h) a plurality ofline selecting means respectively associated with said plurality groupsof data propagation paths, and each selectively connecting the datapropagation paths of the associated group with said read and write bussystem; and i) a diagnostic means associated with said input and outputmeans, and monitoring potential levels on said read and write bus systemin said parallel testing mode to see whether or not the test bitssequentially read out from said predetermined data storage blocks areidentical in logic level for producing said diagnostic signal indicativeof consistence or inconsistence.